The data sheet for a device I'm interested in is not available online. How can I obtain it?
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The device I'm interested in is not listed on the web site. Is it obsolete?
At Data Delay Devices, we continue to support all of our products. Fill out a Contact Us form for more information regarding the device.
What's the difference between a DDU4 and a DDU4F?
The DDU4F is a newer version of the DDU4, which uses a FAST-TTL buffer internally instead of the older S-TTL buffer. This results in faster output signal rise times and lower power consumption. Otherwise, the two devices function identically. The same can be said for any other device whose series ends with the letter F. In applications requiring very short delays and/or very high frequency signals, we suggest that you contact Tech Support for additional information.
What's the difference between a DDU11 and a DDU11H?
The DDU11H is a newer version of the DDU11, which uses a 10KH-ECL buffer internally instead of the older 10K-ECL buffer. Otherwise, the two devices function identically. The same can be said for any other device whose series ends with the letter H. In applications requiring very short delays and/or very high frequency signals, we suggest that you contact Tech Support for additional information.
Are your parts available in surface mount packages?
Nearly all of our parts are available in surface mount packages. Consult the device data sheets for more information.
Do you manufacture Industrial Range (-40C to 85C) devices?
Do you manufacture Military Range (-55C to 125C) devices?
On all military-grade products, complete MIL qualification tests and test reports are available at cost on a part-by-part basis when specifically called out on the purchase order (P/O). Requests for qualification testing and/or test reports must be imposed prior to P/O acceptance. Data Delay Devices does not participate in a QPL style qualification program that can establish qualification on a series of parts.
Commercial Off-The-Shelf (COTS) military-grade devices are identified with the suffix M (e.g. DDU7F-100M), whereas custom military-grade devices are assigned a unique part identification number. All of the components in our military-grade assemblies meet their respective MIL-Specs, and the internal IC's on active military-grade modules are screened to MIL-STD-883. Our assembled military products have in the past been capable of meeting or exceeding all the environmental requirements of MIL-D-23859 (passive and active devices), MIL-D-83531 (passive devices) and MIL-D-83532 (active devices). They are currently capable of meeting or exceeding all the environmental requirements of MIL-PRF-83531 (passive devices) or MIL-PRF-83532 (active devices).
COTS military-grade monolithic microcircuits are identified with the suffix M (e.g. 3D7005-100M), whereas custom military-grade microcircuits are assigned a unique part identification number. Our monolithic military products are capable of meeting or exceeding all the requirements of MIL-STD-883, Method 5004, Class level B screening and MIL-STD-883, Method 5005, Class level B quality conformance inspection. Please note that military-grade monolithic products are available on most device configurations, but may incur significant setup costs and will require significant lead times.
Do your ECL parts work at -5.00V or -5.20V? Can they be operated in PECL mode?
Our ECL parts work at both -5.00V and -5.20V, and can be operated in PECL mode.
Are your delay increment specifications guaranteed?
The delay increment specification is a design goal and may not be satisfied over the complete range of addresses (in the case of PDU's) or taps (in the case of DDU's and passive devices). However, monotonicity is always guaranteed. We can screen devices in order to guarantee the increment everywhere; however, in most cases this would be considered a custom part. The exception is with all of our standard monolithic products, for which all increments are guaranteed to be within tolerance.
The total delay tolerance and the increment tolerance for some units appear to be incompatable. Why is that?
The delay tolerances published can often be confusing. Take for example the 1507-100A, with an increment of 10ns+/-2 ns and a total delay of 100ns+/-5ns. According to these specifications alone, there could exist (in theory) a unit with increments of 12ns over the first six taps and increments of 8ns over the last four taps. In this highly unlikely case, the device would exhibit a delay of 104ns on the last tap (within tolerance) and 72ns on the sixth tap (12ns in high), and still be within spec. With the exception of our monolithic devices, only the last tap is required to have a delay within tolerance. We can screen devices in order to guarantee the delay at all taps; however, in most cases this would be considered a custom part.
How much jitter can I expect from a digitally buffered delay line?
Data Delay Devices does not provide jitter specifications. In general, however, there are two sources of jitter. The first is generated by the buffers, and the associated jitter figures can be obtained from standard IC documentation. The second is delay-dependent and is associated with the rise-time of the internal delay line. The longer the rise time, the more sensitive the delay will be to external noise sources. If your application is particularly sensitive to jitter, we suggest that you contact Tech Support and describe your requirements in detail.
What's the difference between the Recommended, Suggested and Absolute Minimum Input Pulse Width?
The Recommended minimum input pulse width is a performance constraint. If it is satisfied, then the delay specifications are guaranteed. If the input pulse width is less than the Recommended width but greater than the Suggested width, certain taps or addresses may be out of tolerance. In the case of very small increments, monotonicity may even be violated at isolated points. However, the signal will still pass through the device with minimal distortion. Below the Suggested width, the signal will begin to deteriorate significantly, and below the Absolute width, no output should be expected.
It should be noted that the minimum pulse requirements apply to both the width of the high and low portions of the signal. As a result, the minimum input period is given by twice the minimum pulse width, provided that the signal has a 50% duty-cycle.
Although the delays observed at these higher frequencies may deviate from their values under low-frequency operation, once a period and pulse width are given, the delay will not change from one cycle to the next. In other words, there will be no additional jitter due to operation at a fixed high frequency.
What is the frequency response of a passive delay line?
A passive delay line is essentially a low-pass filter with extremely linear phase response in the passband and a very sharp cutoff. Theoretically, the frequency response of a delay line (in MHz) is given by 350 divided by the rise time of the line (in ns). In some cases, the rise time of each device is listed explicitly on the data sheet. More often, however, only the delay-to-rise-time ratio (TD/TR) is given, from which the rise time can be determined. For example, the 2211-200B has a delay of 200ns and a TD/TR of 10. Therefore, the rise time is 20ns and the frequency response is 17.5MHz. It should be noted that for very small delays the theoretical bandwidth is often not quite attainable due to the non-ideal properties of the inductors and capacitors used in manufacturing, as well as parasitic effects associated with circuit layout.
The signal coming out of a passive delay line looks awful. What am I doing wrong?
Chances are, the device is not terminated properly. The output of the line must see an impedance equal to the characteristic impedance (Z0) of the line itself. This impedance must be constant over the bandwidth of the line. In most applications, the output of the line is connected to a very high impedance input stage. In such cases, it suffices to connect a fixed resistor equal to Z0 from the delay line output to ground.
The signal fidelity can be improved even further by impedance matching the input of the line. The line should see an impedance of Z0 looking back into the driver. Typically, if a low-impedance driver is used, a series resistor of value Z0 is placed between the driver and delay line input. It should be noted that impedance matching at the input results in approximately 6dB of signal attenuation. If this cannot be tolerated, then the delay line should be driven directly from a low-impedance source.
If a tapped delay line is being used, only the output of the line is to be terminated, and all taps must go to high-impedance inputs. The same hold for mechanically variable lines - the fixed output must be terminated, while the variable tap should see as high an impedance as possible.
How much signal distortion/attenuation should I expect from a passive delay line?
Distortion is defined as the amount of ringing present on the output of a delay line in response to a step input, and is caused by impedance mismatch. A delay line exhibits constant impedance over its 3dB bandwidth. Above this frequency the impedance becomes unpredictable. Therefore, even a properly terminated line will generate reflections for frequencies above its bandwidth, which will appear as ringing. It is therefore imperative that the input be band-limited in order to minimize this effect.
The low-pass-filtering effect of a passive delay line also increases the rise time of signals passing through it. If the input rise time is known, the output rise time may be computed as the square root of the sum of the squares of the input rise time and the delay line rise time. Thus, a signal with a 5ns rise time passing through a delay line with a rise time of 8ns will emerge from the line with a rise time of approximately 9.4ns.
The signal attenuation of a delay line is determined by its DC resistance (R) in relation to its impedance (Z0). When the device is terminated on its output only, the output signal is scaled by a factor Z0/(Z0+R). When it is terminated on both input and output, the signal is scaled by a factor Z0/(2Z0+R). These hold for all frequencies within the passband of the delay line. Beyond cutoff, the signal is attenuated extremely sharply.
Can I connect passive delay lines end-to-end to get more delay?
It is possible to connect the output of one line directly to the input of another, provided they have the same characteristic impedance. It that case, terminate (with a resistor to ground) the output of the second line only. In general, this is done when a larger delay is desired without sacrificing bandwidth. For example, two 1514-50B devices give 100ns total delay with a bandwidth of 35MHz, while a single 1514-100B device cuts off at 17.5MHz. However, the same performance (35MHz) can also be achieved using a 2211-100B. In general, do not use multiple devices when a single one can be found that will meet the required specifications.
It is always possible to increase delay without sacrificing bandwidth by placing an isolation buffer between the lines. In this manner, any number of lines (with arbitrary impedances) can be placed in series.